#MULTICLOCK DOMAIN PDF#

However, if you don’t specify any hold constraint, the hold check edge moves one clock cycle with respect to the setup check. Here the setup check now has one extra clock cycle of the startClock. Now let’s constraint it for multicycle operation. This is equivalent to specifying `set_multicycle_path 1 -setup -end -from FF1/CP -to FF2/D set_multicycle_path 0 -hold -start -from FF1/CP -to FF2/D` The above figure gives the default setup and hold check edges of a fast-to-slow timing path. `set_multicycle_path 5 -setup -end set_multicycle_path 4 -setup -end`ĬASE2: Fast launch clock and slow capture clock. `set_multicycle_path 3 -setup -end set_multicycle_path 2 -hold -end` Move the hold edge ([ath_multiplier – 1) cycles from the endClock.Į.g. This is the required constraint for a proper timing check. Let’s see what happens if we move the hold edge with respect to the capture clock. Now let’s try setting a hold constraint `set_multi_cycle_path 1 -hold -start` Once you set this, the hold check edge will also move to one clock cycle before the setup check, if you don’t specifically state the hold checking edge. To move this one clock cycle of CLK2, specify `set_multi_cycle_path 2 -setup -end -from FF1/CP -to FF2/D` Here, the red lines show the default setup and hold checking edges without any constraints specified. Here CLK1 and CLK2 are two different frequencies, and multicycle path needs to be set between FF1 & FF2.ĬASE1: Slow launch clock and fast capture clock start/-end options are relevant only for multifrequency paths. (-end is the default) Hold: Regarding to StartClock by Default. Default path_multiplier: Setup 1, Hold 0. end indicates that the multicycle information is relative to the endClock. start indicates that multicycle information is relative to the startClock. `set_multicycle_path -from -to path_multiplier` The SDC command `set_multicycle_path` has an option `-start/-end` that helps in these scenarios. Now let’s explore multicycle paths with two synchronous clock domains of different frequencies. 238000000034 method Methods 0.We have seen set_multicycle_path constraint for timing path within a single clock domain.

Publication of US20060195288A1 publication Critical patent/US20060195288A1/en Status Abandoned legal-status Critical Current Links Assignors: ECKELMAN, JOSEPH E., HUOTT, WILLIAM V., MCNAMARA, TIMOTHY G. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) Filing date Publication date Application filed by International Business Machines Corp filed Critical International Business Machines Corp Priority to US11/056,874 priority Critical patent/US20060195288A1/en Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Original Assignee International Business Machines Corp Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Abandoned Application number US11/056,874 Inventor Timothy McNamara Joseph Eckelman William Huott Current Assignee (The listed assignees may be inaccurate.

#MULTICLOCK DOMAIN PDF#

Google Patents Method for at speed testing of multi-clock domain chipsĭownload PDF Info Publication number US20060195288A1 US20060195288A1 US11/056,874 US5687405A US2006195288A1 US 20060195288 A1 US20060195288 A1 US 20060195288A1 US 5687405 A US5687405 A US 5687405A US 2006195288 A1 US2006195288 A1 US 2006195288A1 Authority US United States Prior art keywords speed clock domain paths test Prior art date Legal status (The legal status is an assumption and is not a legal conclusion. Google Patents US20060195288A1 - Method for at speed testing of multi-clock domain chips US20060195288A1 - Method for at speed testing of multi-clock domain chips

Multiclock domain